A high level modeling system (HLMS) is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. An HLMS provides a higher level of abstraction for describing an electronic circuit than a hardware description language (HDL) simulation environment such as the ModelSim environment from the Model Technology company. An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in a hardware description language (HDL). The Xilinx System Generator tool for DSP and the MathWorks' Simulink and MATLAB environments are example HLMS's.
An HLMS such as System Generator also has the capability to co-simulate a design. Co-simulation generally refers to dividing a design into portions and simulating the portions on two or more platforms. There are different types of platforms on which designs can be co-simulated.
Example co-simulation platforms include both software-based and hardware-based systems. The Modelsim simulator and the NC-SIM simulator from Cadence are example software-based systems, and the Wildcard development platform from Annapolis Microsystems and the Benone development platform from Nallatech are example hardware-based systems. The WildCard and Benone platforms are often used for algorithm exploration and design prototyping.
In a hardware-based system, a portion of the design is emulated on a hardware platform that includes a programmable logic device (PLD), such as a field programmable gate array (FPGA). Co-simulating on a hardware platform may be used to reduce the time required for a simulation run. Co-simulation on a hardware platform may provide limited visibility for the co-simulated portion of the design.
In preparing a design for co-simulation in an HLMS, a designer may face issues of synchronizing the HLMS with a hardware co-simulation platform and having visibility into the state of signals on the hardware platform. To synchronize the software simulation with the hardware simulation, the designer may include ports in the hardware design that can be polled by the HLMS in order to detect when the circuit has reached a particular state. Because the polling is performed asynchronously relative to the hardware, the hardware co-simulation portion of the design is configured to remove sensitivities to timing issues resulting from communication between the software and hardware.
To provide visibility into the state of signals on the hardware platform, a designer may include tracing circuitry in the hardware co-simulation portion of the design. For example, memory blocks may be included to buffer captured data. The issues of synchronization and visibility may unnecessarily complicate the designer's work.
The present invention may address one or more of the above issues.